The present invention relates to integrated circuit (IC) devices, and, in particular, is directed to the packaging of such semiconductor chips.
Packaging is one of the final steps in the process of manufacturing integrated circuits. In packaging, a fabricated IC is mounted within a protective housing. At the present moment, the art of semiconductor chip technology has evolved far more rapidly than the integrally related technology of packaging the integrated circuits.
The packaging requirements of the newer, smaller, more powerful integrated circuits are quickly progressing beyond the capabilities of traditional packaging technology and the conventional materials and designs presently utilized are fast becoming obsolete. The packaging demands of new IC devices require configurations to accommodate increasing numbers of electrical interconnections, space constraints due to decreasing size, reduction in costs, and increasing heat transfer capabilities.
One means of packaging an integrated circuit is to encapsulate the IC in a plastic material. Plastic packages, introduced decades ago, currently are utilized to package the vast majority of integrated circuits in the semiconductor chip industry. A typical area array plastic packaging operation involves the following sequence of steps:
1. In order to hold the chip in place, it first is bonded, generally using an epoxy, to a multilayer laminate substrate, composed of plastic insulator and conductive wiring layers. PA1 2. The chip, held in place on the substrate, then is wire bonded to the substrate wiring layers. PA1 3. The substrate and chip assembly is set within the cavity of a transfer molding fixture and a plastic composition is transferred to fill the cavity, encapsulated the chip, epoxy, bond wires, and substrate top. PA1 4. The encased assembly is removed from the transfer molding fixture, and the array contacts such as pins, ball columns, or land coating are attached. PA1 5. If required for heat dissipation, a heat sink is bonded to the encased assembly.
Wafer scale and real chip size packaging approaches are advantageous in that such packages provide the smallest possible package size for the integrated circuit. However, such customized packages are disadvantageous in their lack of versatility, in that they are limited to the size of the specific chip. Since IC manufacturers' profitability directly is related to the sizes of individual IC chips, reduction in chip sizes is a constant goal and frequently occurs. These reductions in chip sizes commonly impact the circuit board design of the wafer scale or real chip size package customer. Unfortunately, stability over die shrinks is a much needed, but not presently available, feature for these wafer or real chip size type of packages.
Reliability problems in IC packages can occur as the result of the fabrication process for such packages. For area array packages, the reliability of solder joints, in particular, is largely determined by the properties of the substrate to which solder balls are attached; as well as the adhesive layer bonding the substrate to the chip or to the balance of the chip package. To ensure integrity of solder joints, it is essential that there be no discontinuities in the flatness or mechanical stress state of the substrate over the entire package area. Traditional assembly techniques involve dispensing die attach adhesive only on the footprint area of the substrate to which the IC chip will be bonded, setting the chip onto the adhesive or the chip footprint to bond the chip to the substrate, and then encapsulating the chip and substrate package assembly with a thermally set plastic to stabilize the structure. A discontinuity in flatness and stress state results at the edge of the IC chip where the transition is made from the die attach area to the encapsulated area, resulting in potential solder joint reliability issues. As the encapsulated device cools down from the cure temperature of the encapsulant, the larger contraction of the substrate outside of the chip footprint area tends to cause buckling in that area. The mechanical stresses imposed on solder joints by this buckling contributes to early fatigue failure of the solder joints.